1. Field of the Invention
The present invention relates to a capacitive load driving circuit for driving a capacitive load with charging and discharging-currents, such as a capacitive load driving circuit for driving a common electrode of a liquid crystal display panel. Further, the invention relates to a liquid crystal display using a capacitive load driving circuit.
2. Related Art of the Invention
An example of a capacitive load driving circuit for driving a capacitive load composed of a common electrode of a liquid crystal display panel is disclosed in JP-A 2000-174601.
FIG. 3 is a schematic circuit diagram of a capacitive load driving circuit according to the prior art proposed by the present inventors. In this capacitive load driving circuit, as shown in FIG. 3, an output circuit 21 comprises: a power supply terminal 17 connected to a power supply line (Vcc line); a ground terminal 18 connected to a ground line; and an output terminal 16 connected to a capacitive load CL composed, for example, of a common electrode of a liquid crystal display panel.
The output circuit 21 performs selectively a charging-current supplying operation of supplying a charging-current from the output terminal 16 to the capacitive load CL and a discharging-current withdrawing operation of withdrawing a discharging-current from the capacitive load CL to the output terminal 16. The charging-current supplying operation and the discharging-current withdrawing operation are performed selectively depending on the state of a load control input signal S1 the state (high level or low level) of which varies or alternates periodically. The charging-current supplying operation is continued until the voltage of the output terminal 16 reaches an upper amplitude limit. The discharging-current withdrawing operation is continued until the voltage of the output terminal 16 reaches a lower amplitude limit. The output terminal 16, the power supply terminal 17, and the ground terminal 18 are formed into terminal pins for external connection when the capacitive load driving circuit is implemented in the form of an integrated circuit.
FIG. 4 is a circuit diagram showing a specific configuration of the capacitive load driving circuit of FIG. 3.
In the capacitive load driving circuit, when an earth fault (a short circuit to the ground terminal 18) occurs in the output terminal 16, the voltage of the output terminal 16 is always lower than the upper amplitude limit. This causes a large current to flow ceaselessly through a route connecting the power supply terminal 17, a charging output transistor Q1, the output terminal 16, and the ground terminal 18 in this order, during the period that the load control input signal S1 is high.
Similarly, when a sky fault (a short circuit to the power supply terminal 17) occurs in the output terminal 16, the voltage of the output terminal 16 is always higher than the lower amplitude limit. This causes a large current to flow ceaselessly through a route connecting the power supply terminal 17, the output terminal 16, a discharging output transistor Q2, and the ground terminal 18 in this order, during the period that the load control input signal S1 is low.
As such, in case of an earth fault or a sky fault, an excessive current or overcurrent flows in the output circuit 21. This causes the problem of overheat in the output transistors Q1 and Q2 constituting the output circuit 21 and hence in the integrated circuit containing the capacitive load driving circuit comprising the output transistors Q1 and Q2.
Such an earth fault or sky fault occurs, for example, when terminal pins provided in the integrated circuit package containing the capacitive load driving circuit form a short circuit between them. Here, these terminal pins correspond to the output terminal, the power supply terminal, and the ground terminal. Such a short circuit between the terminal pins occurs, for example, owing to an error during the fabrication or owing to the adhesion of electrically conductive dust or the like to the terminal pins during thus